1. Field of the Invention
This invention relates to providing integrated circuits (xe2x80x9cICsxe2x80x9d) with better broadband low impedance power feed than is possible with conventional IC bypass capacitor placement, and more particularly for effectiveness of bypass capacitors used with land grid array (xe2x80x9cLGAxe2x80x9d) or pin grid array (xe2x80x9cPGAxe2x80x9d) packaged high pin density ICs.
2. Related Art
Integrated circuits commonly include a number of metal-oxide-semiconductor (xe2x80x9cMOSxe2x80x9d) transistors, bipolar transistors, diodes and/or other devices fabricated on a semiconductor substrate die that may ultimately be encapsulated within a protective package. Some nodes within the IC require external power supply voltages, ground, and signal connections. Such nodes are coupled within the encapsulation to IC pads to which with solder balls, pads, or the like may be attached. In this fashion, externally provided voltages and signals are coupled to the IC.
FIG. 1, for example, depicts a socketed assembly 10 that includes an IC 20 with associated solder balls 30-1, 30-2 . . . 30-10 mounted on a land grid array (xe2x80x9cLGAxe2x80x9d) package 40, typically ceramic or a plastic material, depending upon ambient temperature specifications. The invention described later herein is also suitable for pin grid array (xe2x80x9cPGAxe2x80x9d) packages and as used herein, the term LGA will be understood to also include PGA.
The upper surface 50 of LGA package 40 will define a number of component conductive pads 60-1, . . . 60-10 that make electrical connection to the IC package solder balls when IC 20 is mounted to the LGA package, e.g., by soldering. Within LGA package 40 conductive planes are formed such as Vcc plane 70 used to carry operating potential Vcc, and Vss plane 80 used to carry a reference potential Vss that is often ground. LGA package 40 may include more than two conductive planes 70, 80 and typically will have a thickness (measured between surfaces 50 and 110) in the range of perhaps 1 mm to 6 mm. The length and width of the LGA package may be 50 mmxc3x9750 mm or larger.
Vertically formed electrically conductive vias such as 90-1, 90-4, 90-5, 90-10 are formed within package 40. These vias permit chosen component conductive pads 60-1, 60-4, 60-5, 60-10 on surface 50 of LGA 40 to make desired electrical connection to Vcc plane 70, or Vss plane 80, and/or LGA mounting pads 100-1, 100-4, 100-5, 100-10 on lower surface 110 of LGA 40. The fabrication of such vias is well known in the relevant art, and will not be described herein.
In FIG. 1A, solder balls 30-1 and 30-10 are coupled internally to nodes formed on IC 20 carrying input or output signals. Solder balls 30-1 and 30-10 make electrical connection to conductive pads 60-1 and 60-10 on the upper surface of the LGA package. In turn, these conductive pads make electrical contact respectively with vias 90-1 and 90-10 to respective LGA mounting pads 100-1 and 100-10 on the lower surface of the LGA package. Because vias 90-1 and 90-10 carry input or output signals, these vias pass through openings in planes 70 and 80 without making electrical contact to either plane.
Solder balls 30-4 and 30-5 are electrically coupled internally to nodes on IC 20 that require Vcc-and Vss potential, respectively. Thus, solder balls 30-4 and 30-5 are respectively electrically coupled to conductive pads 60-4 and 60-5 on the upper surface of the LGA package. Pad 60-4 is electrically coupled to Vcc plane 70 (but not to Vss plane 80) with via 90-4 and to LGA mounting pad 100-4 on the lower surface 110 of the LGA package. Similarly pad 60-5 is electrically coupled to Vss plane 80 (but not to Vcc plane 70) with via 90-5 and to LGA mounting pad 100-5 on the lower surface of the LGA package.
In use, LGA package 40 is inserted into an LGA socket 120 that is mounted to a motherboard or other substrate 130 that provides IC 20 with Vcc, Vss, and input and output signal access through socket contacts 140-1, 140-4, 140-5, 140-10. Socket 120 commonly is shaped as a rectangular or square frame with socket contacts including 140-1, 140-2, etc. located on the socket periphery. As such, a square or rectangular opening (or at least a recess) 150 is defined in the lower central portion of the socket.
In practice, IC 20 may include circuitry requiring relatively noise-free potential at Vcc and Vss component conductive pads 60-4, 60-5 for reliable IC operation. By noise-free, it is meant that ideally signals at these pads should be pure DC, with essentially no AC transient components or crosstalk-coupled components. Some Ics are notorious for generating electrical noise. For example, high speed digital ICs exhibit rapid voltage and current transitions that can produce unwanted current surges and voltage spikes at the Vcc and Vss component conductive pads.
It is known in the art to reduce such noise on Vcc and Vss component conductive pads by coupling one or more bypass capacitors in shunt with these pads. Thus, in
FIG. 1, it is common to dispose one or more bypass capacitors 160, 170 on upper surface 50 of LGA 40. The capacitors make electrical connection through solder balls (or the like) 30-20, 30-21, 30-22, 30-23 to capacitor component conductive pads 60-20, 60-21, and 60-22, and 60-23, and then through vias 90-20, 90-21, and 90-22, 90-23 to the Vcc plane 70 and the Vss plane 80 respectively. Ideally, each capacitor represents a low shunt impedance to high frequency transients, while representing a high shunt impedance to DC voltages.
Bypass capacitors 160, 170 may be in the 0.1 xcexcF range, depending upon the noise susceptibility characteristics of the IC(s) being bypassed. Typical dimensions for a conventional off-the-shelf 0.1 xcexcF bypass capacitor are in the range of perhaps 6 mmxc3x973 mm surface area, by 0.8 mm height.
Unfortunately, the mounting configuration for bypass capacitors 160, 170 shown in FIG. 1 is less than optimum to provide substantially noise-free signals for IC 20 at component conductive pads 60-4, 60-5. Simply stated, the horizontal and lateral electrical path lengths between the capacitors and the nodes being bypassed are too long, with the result that the effective (undesired) parasitic series inductance (Leff) is too large. Consider the path length from capacitor 160 to component conductive pad 60-4. The height of via 90-22 may be a few mm, the lateral separation of via 90-22 from via 90-5 may be 30 mm, and the distance along via 90-5 upward to pad 60-5 will be a few mm, a total distance of perhaps 35 mm or more.
As shown in FIG. 1B, effective bypassing is compounded by the fact that at high frequencies, the Vcc, Vss conductive paths, e.g., 70, 80, may themselves be equivalent to a distributed series of series-coupled parasitic resistor (R) and inductor (L) combinations with parasitic capacitance shunts (C) at the equivalent coupling nodes. Further, the various bypass capacitors, e.g., 160, 170, have parasitic resistance Rs and inductance Ls coupled in series with the capacitor leads. In FIG. 1B, the connection linkage path from IC 20 to bypass capacitor 160 (or 170) is shown with bold lines for emphasis. It will be appreciated that at high currents and/or high frequencies, L1, R1, C1, L2, R2, C2 in the linkage paths, as well as Rs and Ls can degrade the effectiveness of the bypass capacitor 160 or 170. A more detailed discussion of circuit models of parasitic components that can affect capacitor bypassing may be found in the treatise Digital Systems Engineering by W. J. Dally and J. W. Poulton, published by Cambridge University Press, especially portions of Chapter 5 therein.
The relatively long linkage path length between the bypass capacitor and an IC node to be bypassed, shown with bold lines in FIG. 1B, contributes to the overall effective parasitic inductance (Leff), resistance (Reff), and associated shunt capacitance (Cshunt) seen by bypass capacitor 160 or 170. A non-zero value of Leff undesireably increases the magnitude of current-induced voltage spikes (E), often termed xe2x80x9cground bouncexe2x80x9d, according to the relationship:                     E        ≈                              L            eff                    ·                                    δ              ⁢                              xe2x80x83                            ⁢              i                                      δ              ⁢                              xe2x80x83                            ⁢              t                                                          (        1        )            
It is further seen from equation (1) that the magnitude of xcex4i/xcex4t increases with higher switching speeds (e.g., smaller xcex4t) associated with digital ICs. In general, increasing the effective value C of a bypass capacitor (e.g., 160, 170 in FIG. 1) preferably is accomplished by parallel-coupling a number of smaller valued capacitors. This configuration parallel-couples the series inductance associated with each of these capacitors, and the result is a more effective bypass than if a single larger value C were used. Ideally, the nominal impedance (Z) of a bypass capacitor (C) would vary inversely with frequency (xcfx89) according to the relationship:
Z=1/jxcfx89C, where j=xe2x88x921)xe2x80x83xe2x80x83(3)
Unfortunately, real capacitors have associated with them a series inductance and a series resistance. The effective impedance presented by a real capacitor can never be less than its series resistance. But at high frequencies, the Vcc and Vss planes can act as radial transmission lines. The result is that a higher than ideal impedance is presented for each bypass capacitor, due to an upward transformation by these planes, as seen from the connector power and ground pins on the die of IC 20. From equation (3) it is evident that this upward transformation is tantamount to a reduction in the effectiveness of bypass capacitor C.
Associated with a given capacitor C will be a self resonant frequency xcfx89O given by:                               ω          o                =                  1                                                    L                eff                            ·              C                                                          (        4        )            
where Leff is effective inductance seen by the bypass capacitor. The significance of equation (4) is that effective bypassing occurs in a frequency band in which the combination of Leff and C has an impedance that is substantially less than the effective series resistance (ESR). However, it will be appreciated from the foregoing that Leff decreases self-resonant frequency xcfx89O, This is inapposite to the design goal of producing a broadband bypass power feed, characterized by a broadband low impedance and a high xcfx89O, since above the self-resonant frequency, effective capacitor bypassing simply does hot occur.
From equations (1) and (2) it will be appreciated that more effective bypassing could result from mounting one or more bypass capacitors on the IC itself. Indeed U.S. Pat. No. 5,629,240 (1997) to Malladi et al. discloses a method for directly attaching a bypass capacitor to the IC itself, thus substantially reducing the path length of the connecting linkages (L1, R1, C1, L2, R2, C2), and thus reducing Leff. Chip package constraints limit the magnitude of Malladi""s on-chip bypass capacitor to perhaps 100 nF. However, the Malladi patent highlights the need to reduce series inductance in providing an effective bypass capacitor. For purposes of the present invention, IC 20 cannot be modified to include a Malladi-type direct attachment of a bypass capacitor to IC 20.
In short, there is a need for a more effective technique for mounting a bypass capacitor for use with a socket-mounted LGA package (or a PGA package). Preferably such mounting should be useable with conventional off-the-shelf bypass capacitors, and should be implemented using standard LGA fabrication and mounting processes. The mounting should improve the impedance characteristics of the linkage paths between the bypass capacitor and the IC nodes to be bypassed, especially by reducing the effective series inductance seen by the bypass capacitor. Further, effective series inductance is reduced by disposing connecting vias and pads that effectively spread the current carried by the multiple source and return vias by minimizing the current loop area, which is to say, to reduce the energy stored in the effective inductance magnetic field. The resultant LGA mounted IC should see a lower impedance broadband power feed than would be available using prior art bypass capacitor mounting methods.
The present invention provides such mounting of bypass capacitors.
Switching and other transient noise appearing at component mounting pads on an LGA (or PGA) packaged IC are reduced by mounting one or more bypass capacitors beneath the package. The LGA package with bypass capacitors so attached plugs into an LGA (or equivalent) socket, such that the capacitors are disposed within the socket recess or opening. The LGA package includes at least a Vcc plane and a Vss plane. IC nodes to be bypassed are coupled with vias to an underlying bypass capacitor attached to the LGA package lower surface. Because a bypass capacitor may now be disposed beneath the IC to be bypassed, there are substantially no horizontal components in the linkage lead paths between a bypass capacitor and the IC nodes to be bypassed. The capacitor-coupling vias and pads that carry current effectively minimize the current loop area, which is equivalent to reducing the energy stored in the magnetic field of the effective inductance. Since stored energy is proportional to Leff, the result decreases Leff, which increases the capacitor self-resonance frequency. The resultant lower bypass impedance is characterized by a broader band low impedance power feed at the IC than would be possible using conventional above-LGA package bypass capacitor mounting techniques.
Electrical connections between the IC Vcc and Vss pads and a sub-LGA package mounted bypass capacitor are made with spaced-apart first and second vias. The horizontal distance between the vias corresponds to the spaced-apart distance between first and second electrical contacts on the bypass capacitor. Thus, the first via couples one capacitor contact to the Vcc plane and to at least one IC Vcc component mounting pad. Similarly, the second via couples the second capacitor contact to the Vss plane and to at least one IC Vss component mounting pad. Because the bypass capacitor may be disposed beneath the IC, total path length from the IC to the bypass capacitor is essentially the vertical height of the connecting via, lateral path lengths are eliminated. Where necessary, a preferably sub-mm offset in a via may be provided, to accommodate spacing between electrical contacts on the bypass capacitor.
Multiple bypass capacitors may be used to bypass a common IC node, and multiple vias may be used for each capacitor connection. Conventional off-the-shelf bypass capacitors may be used, including capacitors used to bypass an IC chip that has an attached connector. Where necessary, the LGA socket may be modified to accommodate excessively thick bypass capacitors by deepening any recess.
Other features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail, in conjunction with the accompanying drawings.